1. Field of the Invention
The present invention relates to overvoltage protection circuits, and more particularly to a method and apparatus for establishing an input voltage sufficient to excite threshold detection circuitry while satisfying device input voltage limit requirements.
2. Description of the Related Art
Over more recent years, integrated circuits (ICs) and their commensurate operating voltages have been scaled to the degree that overvoltage protection is often needed or otherwise desired at the input of a receiver or threshold detection device receiving an input signal that exceeds a maximum input voltage level of the receiver. The Assisted Gunning Transceiver Logic (AGTL) bus, for example, operates at voltage levels in the range of 1.25–1.5 Volts (V) yet may receive higher voltage signals, such as a 3.3V signal from a power supply having a 1V switching threshold or a 2.5V signal having a 1.25V switching threshold. An AGTL input receiver operates using a standard reference bus voltage VTT of 1.5 V with a switching threshold of ⅔ VTT or 1V. More recent AGTL bus specifications contemplate even lower voltage levels, such as a 1.25V bus having a 0.83V reference threshold. AGTL is referenced solely for purposes of illustration; the present invention applies to any threshold detection device or receiver in which it is desired to limit input voltage.
A voltage limit circuit may be included to clamp the maximum voltage applied to a lower voltage input device. A conventional clamp circuit includes an NMOS device having its gate coupled to a source voltage (e.g., VTT), its source receiving the input signal operating within the higher voltage range, and its drain provided to the input of the lower voltage input device. Accordingly, when the input signal increases to a threshold below VTT, the NMOS device turns off, clamping the signal provided to the differential input receiver to a threshold below VTT. VTT is generally the source voltage of the threshold detection device, and may be provided from an external source, such as a bus voltage or the like.
Conventional input over-voltage protection devices, such as the NMOS device just described, may become problematic when these devices clamp input signal voltages too low to reliably excite corresponding threshold detection circuits. For instance, in a system where the source voltage VTT is 1.5V, a conventional NMOS input voltage clamp would clamp the signal provided to the differential input to approximately 1.1V, which is VTT minus the quantity of an NMOS threshold plus body effect. This level is only 0.1V above the 1V threshold voltage for an AGTL configuration. Clamping the input signal to this lower level may not provide for reliable detection of a logic high state of the input signal under operating conditions that include bus noise, thermal gradients, and power supply variation.